Skew-Tolerant Circuit Design (The Morgan Kaufmann Series in Computer Architecture and Design)

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in todays chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their t As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in todays chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers. This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues. • Synthesizes the most recent advances in skew-tolerant design in one cohesive tutorial • Provides incisive instruction and advice punctuated by humorous illustrations • Includes exercises to test understanding of key concepts and solutions to selected exercises Biography David Harris is currently an Assistant Professor of Engineering at Harvey Mudd College. He received his Ph.D. in 1999 from Stanford University on skew-tolerant circuit design. Since receiving his M. Eng. from MIT in 1994, he has consulted and taught in the field of high-speed CMOS circuit design at Sun Microsystems, Intel Corporation, HAL Computer, and Evans & Sutherland. In addition, he has taught circuit design at the UC Berkeley Extension and Stanford University About The Author: David Harris is currently an Assistant Professor of Engineering at Harvey Mudd College. He received his Ph.D. in As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in todays chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their t As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in todays chip designs is clock skew, the uncertainty in arrival times between a... Read More

Categories: Action & Adventure